/* ADF programmer for Attiny 13a. * (c) PE9RX, v1.0 June 2019 * * Please check the ADF435x datasheet or consult ADF435x software for PLL register values. * https://www.analog.com/media/en/technical-documentation/data-sheets/ADF4351.pdf * https://www.analog.com/en/products/adf4351.html * https://www.analog.com/media/en/evaluation-boards-kits/evaluation-software/ADF435x_v4_5_0.zip * * Code for working with the ADF4351. * appliable with the PCB I created. * Standard settings are for LO with 432.500 MHZ IF and suitable for working simplex on the Es'Hail 2 - QO100 sattalite. * * code is partionally from Remco PA3FYM. */ // Referenz=25mhz // TX1 1970MHz bedeutet 1970+430=2400MHz =10 489,500MHz Band Anfang // besser: // TX1 1967.5MHz bedeutet 1969,5+430,5=2400MHz =10 489,500MHz Band Anfang uint32_t regs_25MHz_70cm[6] = {0x4E8070 , 0x80080C9 , 0x4E42 , 0x4B3 , 0x9C803C , 0x580005 } ; // TX2 2255,5.5MHz bedeutet 2255,5+144,5=2400MHz =10 489,500MHz Band Anfang uint32_t regs_25MHz_2m[6] = {0x2D0058 , 0x8008191 , 0x4E42 , 0x4B3 , 0x8C803C , 0x580005 } ; // Referenz=10mhz // TX1 1967.5MHz bedeutet 1969,5+430,5=2400MHz =10 489,500MHz Band Anfang uint32_t regs_10MHz_70cm[6] = {0xC48048 , 0x8008051 , 0x4E42 , 0x4B3 , 0x95003C , 0x580005 } ; // TX2 2255,5.5MHz bedeutet 2255,5+144,5=2400MHz =10 489,500MHz Band Anfang uint32_t regs_10MHz_2m[6] = {0x708058 , 0x80080A1 , 0x4E42 , 0x4B3 , 0x85003C , 0x580005 } ; #define sbi(x,y) x |= _BV(y) // set bit #define cbi(x,y) x &= ~(_BV(y)) // clear bit #define is_high(x,y) (x & _BV(y) == _BV(y)) // check if the y'th bit of register 'x' is high #define le 0 #define data 1 #define clk 2 #define lo 4 //hier Lo- QRG Hi = 70cm Lo = 2m #define ref 3 //hier Ref QRG Hi = 25MHz Lo = 10MHz int LoPinState; int RefPinState; int LoPinState_alt; int RefPinState_alt; void setup() { DDRB |= 0b11100111; // PB4 and PB3 inputs, rest are all outputs, note PB7-6 don't exist on NANO or ATTiny13a PORTB |= 0b00011000; // make PB4 - PB3 high (pull up active) PORTB &= 0b11111000; // make PB2 - PB0 low pinMode(lo, INPUT_PULLUP); pinMode(ref, INPUT_PULLUP); } // setup void loop() { //Pins abfragen LoPinState = digitalRead(lo); RefPinState = digitalRead(ref); //Wenn anderer Pinstatus if((LoPinState != LoPinState_alt)||(RefPinState != RefPinState_alt)) { //Pinstati merken LoPinState_alt = LoPinState; RefPinState_alt = RefPinState; //Register schreiben if (LoPinState) { if (RefPinState) { writePLL(regs_25MHz_70cm[4]); writePLL(regs_25MHz_70cm[3]); writePLL(regs_25MHz_70cm[2]); writePLL(regs_25MHz_70cm[1]); writePLL(regs_25MHz_70cm[0]); } else { writePLL(regs_10MHz_70cm[4]); writePLL(regs_10MHz_70cm[3]); writePLL(regs_10MHz_70cm[2]); writePLL(regs_10MHz_70cm[1]); writePLL(regs_10MHz_70cm[0]); } } else { if (RefPinState) { writePLL(regs_25MHz_2m[4]); writePLL(regs_25MHz_2m[3]); writePLL(regs_25MHz_2m[2]); writePLL(regs_25MHz_2m[1]); writePLL(regs_25MHz_2m[0]); } else { writePLL(regs_10MHz_2m[4]); writePLL(regs_10MHz_2m[3]); writePLL(regs_10MHz_2m[2]); writePLL(regs_10MHz_2m[1]); writePLL(regs_10MHz_2m[0]); } } } } void writePLL(uint32_t pll_word) { // this routine clocks a 24 bits word into the ADF4001 // msb (b32) first, lsb (b0) last for (uint8_t flop=0; flop<32; flop++) { // PLL word has 32 bits pll_word & 0x80000000 ? sbi(PORTB,data):cbi(PORTB,data); // OR / AND with MSB to clock in '1' / '0' on PB1 sbi(PORTB,clk); // clock in bit on rising edge of CLK (PB2 = 1) asm("nop"); cbi(PORTB,clk); // CLK (PB2 = 0) pll_word <<= 1; // rotate left for next bit } // for flop sbi(PORTB,le); // make LE high asm("nop"); cbi(PORTB,le); // make LE low cbi(PORTB,data); } // writePLL